Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Sequential circuit verification using symbolic model checking
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Automatic functional test generation using the extended finite state machine model
DAC '93 Proceedings of the 30th international Design Automation Conference
Diagnosis and correction of logic design errors in digital circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
Architecture validation for processors
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Functional VLSI Design Verification Methodology for the CM-5 Massively Parallel Supercomputer
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Coverage-Directed Test Generation Using Symbolic Techniques
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
A Unified Framework for Design Validation and Manufacturing Test
Proceedings of the IEEE International Test Conference on Test and Design Validity
Sequential Redundancy Identification Using Verification Techniques
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
High-level test generation for design verification of pipelined microprocessors
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Improving coverage analysis and test generation for large designs
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
A Buffer-Oriented Methodology for Microarchitecture Validation
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
An RTL Abstraction Technique for Processor MicroarchitectureValidation and Test Generation
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
Smart simulation using collaborative formal and simulation engines
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Simulation coverage enhancement using test stimulus transformation
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
On Design Validation Using Verification Technology
Journal of Electronic Testing: Theory and Applications
An Automatic Controller Extractor for HDL Descriptions at the RTL
IEEE Design & Test
Effectiveness of Microarchitecture Test Program Generation
IEEE Design & Test
Coverage Metrics for Functional Validation of Hardware Designs
IEEE Design & Test
Symbolic Simulation with Approximate Values
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Coverage Metrics for Temporal Logic Model Checking
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
A Temporal Logic Based Theory of Test Coverage and Generation
TACAS '02 Proceedings of the 8th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Coverage Directed Generation of System-Level Test Cases for the Validation of a DSP System
FME '01 Proceedings of the International Symposium of Formal Methods Europe on Formal Methods for Increasing Software Productivity
Automatic Abstraction for Verification of Timed Circuits and Systems
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
A Practical Approach to Coverage in Model Checking
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Design for Verification at the Register Transfer Level
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Verification of Processor Microarchitectures
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Si-Emulation: System Verification Using Simulation and Emulation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Simulation Using Code-Perturbation: Black- and White-Box Approach
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Fault Models and Test Generation for Hardware-Software Covalidation
IEEE Design & Test
Efficient ATPG for Design Validation Based On Partitioned State Exploration Histories
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Systematic functional coverage metric synthesis from hierarchical temporal event relation graph
Proceedings of the 41st annual Design Automation Conference
Automatic circuit extractor for HDL description using program slicing
Journal of Computer Science and Technology - Special issue on computer graphics and computer-aided design
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
An efficient control-oriented coverage metric
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A coverage metric for the validation of interacting processes
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Verification of embedded systems based on interval analysis
International Journal of Parallel Programming
Coverage metrics for temporal logic model checking
Formal Methods in System Design
A Survey of Hybrid Techniques for Functional Verification
IEEE Design & Test
A new assessment and improvement model of risk propagation in information security
International Journal of Information and Computer Security
Specification-based compaction of directed tests for functional validation of pipelined processors
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Improving functional verification of embedded systems using hierarchical composition and set theory
Proceedings of the 2009 ACM symposium on Applied Computing
MMV: a metamodeling based microprocessor validation environment
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Techniques for abstracting SDL specifications
SAM'02 Proceedings of the 3rd international conference on Telecommunications and beyond: the broader applicability of SDL and MSC
Fast enhancement of validation test sets for improving the stuck-at fault coverage of RTL circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A novel mutation-based validation paradigm for high-level hardware descriptions
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 14.98 |
The enormous state spaces which must be searched when verifying the correctness of, or generating tests for, complex circuits precludes the use of traditional approaches. Hard-to-find abstractions are often required to simplify the circuits and make the problems tractable. This paper presents a simple and automatic method to extract the control flow of a circuit so that the resulting state space can be explored for validation coverage analysis and automatic test generation. This control flow, capturing the essential “behavior” of the circuit, is represented as a finite state machine called the ECFM (Extracted Control Flow Machine). Simulation is currently the primary means of verifying large circuits, but the definition of a coverage measure for simulation vectors is an open problem. We define functional coverage as the amount of control behavior covered by the test suite. We then combine formal verification techniques, using BDDs as the underlying representation, with traditional ATPG techniques to automatically generate additional sequences which traverse uncovered parts of the control state graph. We also demonstrate how the same abstraction techniques can complement ATPG techniques when attacking hard-to-detect faults in the control part of the design for which conventional ATPG alone proves to be inadequate or inefficient at best. Results on large designs show significant improvement over conventional algorithms