Validation coverage analysis for complex digital designs
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Abstraction Techniques for Validation Coverage Analysis and Test Generation
IEEE Transactions on Computers
POPL '80 Proceedings of the 7th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Coverage directed test generation for functional verification using bayesian networks
Proceedings of the 40th annual Design Automation Conference
A coverage metric for the validation of interacting processes
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Writing Testbenches using SystemVerilog
Writing Testbenches using SystemVerilog
Comprehensive Functional Verification: The Complete Industry Cycle (Systems on Silicon)
Comprehensive Functional Verification: The Complete Industry Cycle (Systems on Silicon)
Functional Verification of RTL Designs driven by Mutation Testing metrics
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
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During functional verification, complex interactions between multiple modules that compose a digital circuit design can reveal hard-to-find bugs. Functional coverage specifications must be precise to assure these interactions occur during the simulation. We are proposing a technique for improving the functional verification specification of individual modules, preserving the occurrence of these interactions scenarios in the composition phase. We obtain these new specifications in a deductive way, by means of set theory. Using experimental results, we show how our work can contribute to error detection and save functional verification time.