Formal verification of content addressable memories using symbolic trajectory evaluation
DAC '97 Proceedings of the 34th annual Design Automation Conference
Abstraction Techniques for Validation Coverage Analysis and Test Generation
IEEE Transactions on Computers
DAC '98 Proceedings of the 35th annual Design Automation Conference
Formal verification meets simulation (embedded tutorial) (abstract only)
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
A Technique for Estimating the Difficulty of a Formal Verification Problem
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
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In this paper we introduce a novel concept that can be used for augmenting simulation based verification at the Register Transfer Level (RTL). In this technique the designer of an RTL circuit introduces some well understood extra behavior (through some extra circuitry) into the circuit under verification. This can be termed as design for verification. During RTL simulation this extra behavior is utilized in conjunction with the original behavior to exercise the design more thoroughly thus making it easier to detect errors in the original design. Once the circuit is throughly verified for functionality the extra behavioral constructs can be removed to produce the original verified design. Extensive experiments on a number of industrial circuits demonstrate that the method is promising.