A Technique for Estimating the Difficulty of a Formal Verification Problem

Authors:
Indradeep Ghosh;Mukul R. Prasad
Affiliations:
Fujitsu Laboratories of America, Sunnyvale, CA, USA;Fujitsu Laboratories of America, Sunnyvale, CA, USA
Venue:
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Year:
2006

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Abstract

In this paper a technique is proposed to estimate the level of difficulty of formally verifying an RTL circuit. The technique is based on extensive experimental data generated from a wide range of industrial and academic benchmarks. Statistical as well as intuitive inferences have been drawn from the data to obtain an algorithm that can classify the level of difficulty of formally verifying a property on a particular circuit into five broad categories. The difficulty of verifying the whole circuit is a weighted average of the difficulty of verifying its individual properties. The level of coverage generated by the properties gives us a confidence level on the accuracy of the metric.