Architecture validation for processors
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
What's between simulation and formal verification? (extended abstract)
DAC '98 Proceedings of the 35th annual Design Automation Conference
A Technique for Estimating the Difficulty of a Formal Verification Problem
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Anton, a special-purpose machine for molecular dynamics simulation
Proceedings of the 34th annual international symposium on Computer architecture
Estimating functional coverage in bounded model checking
Proceedings of the conference on Design, automation and test in Europe
Enhancing bug hunting using high-level symbolic simulation
Proceedings of the 19th ACM Great Lakes symposium on VLSI
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Design verification of complex digital circuits typically starts only after the register-transfer level (RTL) description is complete. This frequently makes verification more difficult than necessary because logic that is intrinsically hard to verify, such as memories, counters and deep first-in, first-out (FIFO) structures, becomes immutable in the design. This paper proposes a new approach that exploits formal verification of conditional coverage points with the goal of early identification of hard-to-verify logic. We use the difficulty of formal verification problems as an early estimator of the verification complexity of a design. While traditional verification methods consider conditional coverage only in the design verification phase, we describe an approach that uses conditional coverage at a much earlier stage---the design phase, during which changes to the RTL code are still possible. The method is illustrated using real examples from the verification of an ASIC designed for a specialized supercomputer.