Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Representing circuits more efficiently in symbolic model checking
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
Formal verification by symbolic evaluation of partially-ordered trajectories
Formal Methods in System Design - Special issue on symbolic model checking
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Formal verification in hardware design: a survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 38th annual Design Automation Conference
Handling special constructs in symbolic simulation
Proceedings of the 39th annual Design Automation Conference
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
RTL-Datapath Verification using Integer Linear Programming
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
StressTest: an automatic approach to test generation via activity monitors
Proceedings of the 42nd annual Design Automation Conference
A Survey of Hybrid Techniques for Functional Verification
IEEE Design & Test
Proceedings of the 45th annual Design Automation Conference
Optimizing blocks in an SoC using symbolic code-statement reachability analysis
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Facilitating unreachable code diagnosis and debugging
Proceedings of the 16th Asia and South Pacific Design Automation Conference
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The miniaturization of transistors in recent technology nodes requires tremendous back-end tuning and optimizations, making bug fixing at later design stages more expensive. Therefore, it is imperative to find design bugs as early as possible. The first defense against bugs is block-level testing performed by designers, and constrained-random simulation is the prevalent method. However, this method may miss corner-case scenarios. In this paper we propose an innovative methodology that reuses existing constrained-random testbenches for formal bug hunting. To support the methodology, we present several techniques to enhance RTL symbolic simulation, and integrate state-of-the-art word-level and Boolean-level verification techniques into a common framework called BugHunter. From case studies DLX, Alpha and FIR, BugHunter found more bugs than constrained-random simulation using fewer cycles, including four new bugs in the verified design previously unknown to the designer. The results demonstrate that the proposed techniques provide a flexible, scalable and robust solution for bug hunting.