A Biased Random Instruction Generation Environmentfor Architectural Verification of Pipelined Processors

Authors:
Ta-Chung Chang;Vikram Iyengar;Elizabeth M. Rudnick
Affiliations:
Compaq Computer Corporation, Shrewsbury, MA 01545, USA. ta-chung.chang@compaq.com;Center for Reliable and High-Performance Computing, Department of Electrical & Computer Engineering, University of Illinois, Urbana, IL 61801, USA. vik@crhc.uiuc.edu;Center for Reliable and High-Performance Computing, Department of Electrical & Computer Engineering, University of Illinois, Urbana, IL 61801, USA. liz@uiuc.edu
Venue:
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
Year:
2000

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Abstract

Architectural verification is a critical aspect of themicroprocessor design cycle. In this paper, we presenta design verification environment centered around abiased random instruction generator for simulation-basedarchitectural verification of pipelined microprocessors.The instruction generator uses biases specified by theuser to generate instruction sequences for simulation.These biases are not hard-coded and can thus be changeddepending on the specific areas in the design and typeof design errors being targeted. Correctness checking isachieved using assertion checking and end-of-statecomparison with a high-level architectural model. Severalarchitectural-level errors are introduced into abehavioral model of the DLX processor to investigate theprocessor's response in the presence of design errors.Simulation experiments conducted using the behavioralmodel show that biased random instruction sequencesprovide higher coverage of RTL conditional branches anddesign errors than random instruction sequences ormanually-generated test programs. Furthermore,instruction sequences containing a high percentage ofread-after-write (RAW) and control dependencies are themost useful.