Design of a cycle-accurate user-retargetable instruction-set simulator using process-based scheduling scheme

Authors:
Hoonmo Yang;Moonkey Lee
Affiliations:
Dept. EE., Yonsei University, Seoul, Korea;Dept. EE., Yonsei University, Seoul, Korea
Venue:
CIS'04 Proceedings of the First international conference on Computational and Information Science
Year:
2004

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Abstract

We designed a cycle-accurate user-retargetable instruction-set simulator (UR-ISS) based on architecture description language (ADL) which is suitable for system-on-chip (SoC) design. It uses a new scheduling method based on process control. It is effective for schedulingmulti-cycle instructions and asynchronous events to a pipeline such as interrupts and exceptions frequently found in SoCs. The proposed UR-ISS consists of a byte-code compiler (BCC) and a virtual machine (VM); The BCC translates ADL semantics into byte-codes and the VM executes them. We have investigated that the UR-ISS is 5.5 times faster than HDL models and 2.5 times faster than System-C models on average. We also applied the UR-ISS for CALMRISC32TMduring its development and obtained good results for functional validation.