Measuring the effectiveness of various design validation approaches for PowerPCTM microprocessor arrays

Authors:
L.-C. Wang;M. S. Abadir;J. Zeng
Affiliations:
Somerset PowerPC Design Center, Motorola, Inc., Austin, Texas;Somerset PowerPC Design Center, Motorola, Inc., Austin, Texas;Somerset PowerPC Design Center, IBM, Austin, Texas
Venue:
Proceedings of the conference on Design, automation and test in Europe
Year:
1998

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Abstract

Although several methods for array design validation have been proposed and had great success in the past, little evidence has been reported for the effectiveness of these methods with respect to the detection of design errors. In this paper, we propose a new way of measuring the effectiveness of different validation approaches based on automatic design error injection and simulation. This technique provides a systematic way for the evaluation of the quality of various validation approaches. Experimental results using different validation approaches on recent PowerPC microprocessor arrays will be reported.