Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
The ESTEREL synchronous programming language: design, semantics, implementation
Science of Computer Programming
Architecture validation for processors
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Latch optimization in circuits generated from high-level descriptions
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Abstraction Techniques for Validation Coverage Analysis and Test Generation
IEEE Transactions on Computers
What's between simulation and formal verification? (extended abstract)
DAC '98 Proceedings of the 35th annual Design Automation Conference
Simulation vector generation from HDL descriptions for observability-enhanced statement coverage
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A study in coverage-driven test generation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Symbolic Model Checking
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
A Methodology for Processor Implementation Verification
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
XEVE, an ESTEREL Verification Environment
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Validation of Pipelined Processor Designs Using Esterel Tools: A Case Study
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
The Murphi Verification System
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
A Common Approach to Test Generation and Hardware Verification Based on Temporal Logic
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Fast Sequential ATPG Based on Implicit State Enumeration
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
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We propose a complete methodology for the automatic generation of test cases in the context of digital circuit validation. Our approach is based on a software model of the system to verify in which some modules are written in the Esterel language. An initial test suite is simulated and the state coverage is computed. New test sequences are automatically generated to reach the missing states. We then convert those sequences into system-level test cases (i.e. instruction sequences) by a technique called "pipeline inversion". The method has been applied for the functional validation of an industrial DSP system giving promising results.