The ESTEREL synchronous programming language: design, semantics, implementation
Science of Computer Programming
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Proof, language, and interaction
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Formal Verification of Out-of-Order Execution Using Incremental Flushing
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Decomposing the Proof of Correctness of pipelined Microprocessors
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Automatic verification of Pipelined Microprocessor Control
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Formal Verification of Pipelined Processors
TACAS '98 Proceedings of the 4th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Coverage Directed Generation of System-Level Test Cases for the Validation of a DSP System
FME '01 Proceedings of the International Symposium of Formal Methods Europe on Formal Methods for Increasing Software Productivity
Scenario-based verification in presence of variability using a synchronous approach
Frontiers of Computer Science: Selected Publications from Chinese Universities
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The design of control units of modern processors is quite complex due to many speed-up techniques like pipelining and out-of-order execution. The existing approaches to formal verification of processor designs are applicable to very high level descriptions that ignore timing details of control signals. In this paper, we propose an approach for verification of detailed design of processors. Our approach suggests the use of Esterel language which has rich constructs for succinct and modular description of control. The Esterel simulation tool Xes and verification tools Xeve and FcTools can be used effectively to catch minor bugs as well as subtle timing errors. As an illustration, we have developed an Esterel implementation of DLX pipeline control and verified certain crucial properties.