Scenario-based verification in presence of variability using a synchronous approach

  • Authors:
  • Jean-Vivien Millo;Frédéric Mallet;Anthony Coadou;S. Ramesh

  • Affiliations:
  • INRIA Sophia-Antipolis, Aoste team (INRIA/I3S/CNRS/UNS), Sophia-Antipolis, France 06560;University of Nice Sophia Antipolis, Sophia-Antipolis, France 06900;Global General Motors R&D, India Science Lab, GM Technical Center India, Bangalore, India 560066;Global General Motors R&D, India Science Lab, GM Technical Center India, Bangalore, India 560066

  • Venue:
  • Frontiers of Computer Science: Selected Publications from Chinese Universities
  • Year:
  • 2013

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Abstract

This paper presents a new model of scenarios, dedicated to the specification and verification of system behaviours in the context of software product lines (SPL). We draw our inspiration from some techniques that are mostly used in the hardware community, and we show how they could be applied to the verification of software components. We point out the benefits of synchronous languages and models to bridge the gap between both worlds.