New design error modeling and metrics for design validation
EURO-DAC '92 Proceedings of the conference on European design automation
Modeling and Simulation of Design Errors
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Abstraction Techniques for Validation Coverage Analysis and Test Generation
IEEE Transactions on Computers
On Design Validation Using Verification Technology
Journal of Electronic Testing: Theory and Applications
12.1 Using Verification Technology for Validation Coverage Analysis and Test Generation
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
A Domain Coverage Metric for the Validation of Behavioral VHDL Descriptions
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A Validation Fault Model for Timing-Induced Functional Errors
ITC '01 Proceedings of the 2001 IEEE International Test Conference
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To use simulation for design verification, designers need a confidence measure for a given set of simulation patterns, specifically for cases in which only a subset of the possible patterns is used. The authors derive a measure of design verification coverage based on the number of design errors detected in a theoretical analysis of a circuit. To verify the theoretical analysis, they simulate errors and compare the results.