Sequential circuit verification using symbolic model checking
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Automatic functional test generation using the extended finite state machine model
DAC '93 Proceedings of the 30th international Design Automation Conference
Diagnosis and correction of logic design errors in digital circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
AVPGEN—a test generator for architecture verification
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architecture validation for processors
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
The automatic generation of functional test vectors for Rambus designs
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Validation coverage analysis for complex digital designs
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
An observability-based code coverage metric for functional simulation
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Abstraction Techniques for Validation Coverage Analysis and Test Generation
IEEE Transactions on Computers
CRIS: a test cultivation program for sequential VLSI circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Functional VLSI Design Verification Methodology for the CM-5 Massively Parallel Supercomputer
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Coverage-Directed Test Generation Using Symbolic Techniques
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
A Unified Framework for Design Validation and Manufacturing Test
Proceedings of the IEEE International Test Conference on Test and Design Validity
ITC '98 Proceedings of the 1998 IEEE International Test Conference
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
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Despite great advances in the area of Formal Verificationduring the last ten years, simulation is currently the primary meansfor performing design verification. The definition of an accurateand pragmatic measure for the coverage achieved by a suite ofsimulation vectors and the related problem of coverage directedautomatic test generation are of great importance. In this paper weintroduce a new set of metrics, called the Event Sequence CoverageMetrics (ESCMs). Our approach is based on a simple and automaticmethod to extract the control flow of a circuit so that the resultingstate space can be explored for validation coverage analysis andautomatic test generation. During simulation we monitor, in additionto state and transition coverage, whether certain control eventsequences take place or not. We then combine formal verificationtechniques, using BDDs as the underlying representation, withtraditional ATPG and behavioral test generation techniques toautomatically generate additional sequences which traverse uncoveredparts of the control state graph, or exercise an uninstantiatedcontrol event sequence.