Automatic functional test generation using the extended finite state machine model
DAC '93 Proceedings of the 30th international Design Automation Conference
Architecture validation for processors
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Validation coverage analysis for complex digital designs
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
An observability-based code coverage metric for functional simulation
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Coverage-Directed Test Generation Using Symbolic Techniques
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
A Unified Framework for Design Validation and Manufacturing Test
Proceedings of the IEEE International Test Conference on Test and Design Validity
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Despite great advances in Formal Verification (FV), simulation is still the primary means for design validation. The definition of pragmatic measures for the coverage achieved and the problem of automatic test generation(ATG) are of great importance. In this paper we introduce a new set of metrics, the Event Sequence Coverage Metrics (ESCMs). Our approach is based on an automatic method to extract the control flow of a circuit which can be explored for coverage analysis and ATG. We combine FV and traditional ATPG techniques to automatically generate sequences which traverse uncovered parts of the control graph or exercise uninstantiated control event sequences.