ISDL: an instruction set description language for retargetability
DAC '97 Proceedings of the 34th annual Design Automation Conference
Abstraction Techniques for Validation Coverage Analysis and Test Generation
IEEE Transactions on Computers
Advanced compiler design and implementation
Advanced compiler design and implementation
EXPRESSION: a language for architecture exploration through compiler/simulator retargetability
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Simulation vector generation from HDL descriptions for observability-enhanced statement coverage
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Model checking
Validating the intel pentium 4 microprocessor
Proceedings of the 38th annual Design Automation Conference
LISA: A Specification Language Based on WS2S
CSL '97 Selected Papers from the11th International Workshop on Computer Science Logic
Functional Coverage Driven Test Generation for Validation of Pipelined Processors
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Intel Virtualization Technology
Computer
Designing Digital Computer Systems with Verilog
Designing Digital Computer Systems with Verilog
EWD: A metamodeling driven customizable multi-MoC system modeling framework
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Metamodeling-rapid design and evolution of domain-specific modeling environments
ECBS'99 Proceedings of the 1999 IEEE conference on Engineering of computer-based systems
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With increasing levels of integration of multiple processing cores and new features to support software functionality, recent generations of microprocessors face difficult validation challenges. The systematic validation approach starts with defining the correct behaviors of the hardware and software components and their interactions. This requires new modeling paradigms that support multiple levels of abstraction. Mutual consistency of models at adjacent levels of abstraction is crucial for manual refinement of models from the full chip level to production register transfer level, which is likely to remain the dominant design methodology of complex microprocessors in the near future. In this paper, we present microprocessor modeling and validation environment (MMV), a validation environment based on metamodeling, that can be used to create models at various abstraction levels and to generate most of the important validation collaterals, viz., simulators, checkers, coverage, and test generation tools. We illustrate the functionalities in MMV by modeling a 32-bit reduced instruction set computer processor at the system, instruction set architecture, and microarchitecture levels. We show by examples how consistency across levels is enforced during modeling and also how to generate constraints for automatic test generation.