IEEE Transactions on Software Engineering - Special issue on formal methods in software practice
Abstraction Techniques for Validation Coverage Analysis and Test Generation
IEEE Transactions on Computers
Symbolic model checking using SAT procedures instead of BDDs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Model checking
Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques
Proceedings of the 37th Annual Design Automation Conference
LPSAT: a unified approach to RTL satisfiability
Proceedings of the conference on Design, automation and test in Europe
Interval-Based Analysis of Software Processes
OM '01 Proceedings of the 2001 ACM SIGPLAN workshop on Optimization of middleware and distributed systems
Symbolic Model Checking
BerkMin: A Fast and Robust Sat-Solver
Proceedings of the conference on Design, automation and test in Europe
Functional vector generation for HDL models using linear programming and Boolean satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Assertion Checking of Behavioral Descriptions with Non-linear Solver
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Verification of embedded systems based on interval analysis
International Journal of Parallel Programming
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The 2001 International Technology Roadmap for Semiconductors (ITRS) predicts that it is unlikely that verification will be manageable for designs envisioned beyond 2007 without design-for-verifiability. Some CAD vendors have promoted assertion-based verification (ABV) as one of the first commercial design-for-verification techniques. In order to handle complex design, this methodology has to be complemented with tools that automatically generate vectors or counterexamples that violate/verify proposed assertions or constraints. This paper presents an assertion checking technique for behavioral models that combines a non-linear solver and state exploration techniques and avoids expanding behavior into logic equations. The kernel of the technique is a modified interval analysis (MODIA) that avoids most of the problems of classical interval analysis (IA) and improves reuse during vector generation. The results show that the proposed technique is able to handle very efficiently data-dominated designs, which research and commercial assertion/property checkers are unable or need more CPU effort to verify.