IEEE Transactions on Software Engineering - Special issue on formal methods in software practice
Abstraction Techniques for Validation Coverage Analysis and Test Generation
IEEE Transactions on Computers
Polynomial methods for allocating complex components
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Model checking
Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques
Proceedings of the 37th Annual Design Automation Conference
LPSAT: a unified approach to RTL satisfiability
Proceedings of the conference on Design, automation and test in Europe
Symbolic Model Checking
Behavioral Intervals in Embedded Software: Timing and Power Analysis of Embedded Real-Time Software Processes
BerkMin: A Fast and Robust Sat-Solver
Proceedings of the conference on Design, automation and test in Europe
Advanced Formal Verification
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Complex instruction and software library mapping for embedded software using symbolic algebra
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The latest versions of the "International Technology Roadmap for Semiconductors" (ITRS) highlight that verification has changed from playing a relatively minor supporting role in the design process to becoming the dominant cost. This situation is the result of the exponential growth of the functional complexity of designs and the historical emphasis of CAD tools in other areas of the design process such as automatic synthesis or place-and-route. The problem is even worst in embedded systems that normally integrate functionally complex hardware and software parts. This work presents a new verification technique based on interval analysis that can handle embedded designs described at behavioural level. The proposed technique is able to verify assertions that the users insert in software and hardware tasks. It shows very promising results in systems that cannot be efficiently verified with other tools (e.g. data-dominated designs).