Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Instruction level power analysis and optimization of software
Journal of VLSI Signal Processing Systems - Special issue on technologies for wireless computing
Combining multiple models of computation for scheduling and allocation
Proceedings of the 6th international workshop on Hardware/software codesign
Communication estimation for hardware/software codesign
Proceedings of the 6th international workshop on Hardware/software codesign
Representation of process mode correlation for scheduling
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Bounding Pipeline and Instruction Cache Performance
IEEE Transactions on Computers
Resolution of dynamic memory allocation and pointers for the behavioral synthesis form C
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Execution cost interval refinement in static software analysis
Journal of Systems Architecture: the EUROMICRO Journal - Modern methods and tools in digital system design
Performance Analysis of Real-Time Embeded Software
Performance Analysis of Real-Time Embeded Software
Parametric Dispatching of Hard Real-Time Tasks
IEEE Transactions on Computers
On Predicting Data Cache Behavior for Real-Time Systems
LCTES '98 Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems
Integrating Path and Timing Analysis Using Instruction-Level Simulation Techniques
LCTES '98 Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems
Data flow based cache prediction using local simulation
HLDVT '00 Proceedings of the IEEE International High-Level Validation and Test Workshop (HLDVT'00)
Path clustering in software timing analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Processor Pipelines and Their Properties for Static WCET Analysis
EMSOFT '02 Proceedings of the Second International Conference on Embedded Software
SPI: a system model for heterogeneously specified embedded systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Exploiting Dynamic Workload Variation in Low Energy Preemptive Task Scheduling
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
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A typical characteristic of complex embedded systems is their large software share that consists of software processes either being directly written in an implementation language like C, or being created from abstract modeling tools (e. g. Simulink or StateMate) using standard code generators, or being reused from previous designs (e. g. legacy code). A major challenge is the safe integration of these separately designed system parts. This paper focuses on the formal analysis of software processes with respect to their non-functional properties like timing or power consumption. The proposed approach yields safe upper and lower bounds on these properties and has advantages over previous work in terms of accuracy and efficiency. Further, it is shown how the results of this process-level analysis can be utilized to generate a model for the system-wide validation of non-functional properties. The applicability of the approach is demonstrated using an example of a filter process operating on a packet stream.