Reduced instruction set computer architectures for VLSI
Reduced instruction set computer architectures for VLSI
Scheduling expressions on a pipelined processor with a maximal delay of one cycle
ACM Transactions on Programming Languages and Systems (TOPLAS)
Matrix multiplication via arithmetic progressions
Journal of Symbolic Computation - Special issue on computational algebraic complexity
Instruction scheduling for the IBM RISC System/6000 processor
IBM Journal of Research and Development
Scheduling time-critical instructions on RISC machines
ACM Transactions on Programming Languages and Systems (TOPLAS)
Single machine scheduling subject to precedence delays
Discrete Applied Mathematics
Efficiency of a Good But Not Linear Set Union Algorithm
Journal of the ACM (JACM)
Scheduling Tasks with Nonuniform Deadlines on Two Processors
Journal of the ACM (JACM)
An Almost-Linear Algorithm for Two-Processor Scheduling
Journal of the ACM (JACM)
Postpass Code Optimization of Pipeline Constraints
ACM Transactions on Programming Languages and Systems (TOPLAS)
The Design and Analysis of Computer Algorithms
The Design and Analysis of Computer Algorithms
A Fast Algorithm for Scheduling Time-Constrained Instructions on Processors with ILP
PACT '98 Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques
Deterministic Scheduling with Pipelined Processors
IEEE Transactions on Computers
IBM Journal of Research and Development
Fast Optimal Instruction Scheduling for Single-Issue Processors with Arbitrary Latencies
CP '01 Proceedings of the 7th International Conference on Principles and Practice of Constraint Programming
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In this paper, We propose a faster algorithm for the following instruction scheduling problem: Given a set of UET (Unit Execution Time) instructions with precedence constraints in the form of a DAG(Directed Acyclic Graph), latency constraints where latencies between any two instructions are restricted to be either 0 or 1, timing constraints in the form of individual integer release times and deadlines and a single RISC processor, find a feasible schedule which satisfies all constraints. The time complexity of our algorithm is O(n2 log n) + min{O(ne), O(n2.376)}, where n is the number of instructions and e is the number of edges in the precedence graph. Our algorithm is faster than the existing algorithm which runs in O(n3α(n)) time, where α(n) is the inverse of Ackermann function. In addition, our algorithm can be used to solve the maximum lateness minimization problem in O(n2 log2 n + min{ne, n2.376}) time.