RISC I: A Reduced Instruction Set VLSI Computer
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
Comments on "A Massive Memory Machine"
IEEE Transactions on Computers
IEEE Transactions on Computers
Incorporating data flow ideas into von neumann processors for parallel execution
IEEE Transactions on Computers
Instruction Scheduling with Timing Constraints on a Single RISC Processor with 0/1 Latencies
CP '02 Proceedings of the 6th International Conference on Principles and Practice of Constraint Programming
A GaAs-Based Microprocessor Architecture for Real-Time Applications
IEEE Transactions on Computers
Compilers, architectures and synthesis for embedded computing: retrospect and prospect
CASES '10 Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems
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This paper provides an overview of an experimental system developed at the IBM Thomas J. Watson Research Center. It consists of a running hardware prototype, a control program, and an optimizing compiler. The basic concepts underlying the system are discussed, as are the performance characteristics of the prototype. In particular, three principles are examined: (1) system orientation towards the pervasive use of high-level language programming and a sophisticated compiler, (2) a primitive instruction set which can be completely hard-wired, and (3) storage hierarchy and I/O organization to enable the CPU to execute an instruction at almost every cycle.