A GaAs-Based Microprocessor Architecture for Real-Time Applications

Authors:
V. Milutinovic;N. Lopez-Benitez
Affiliations:
School of Electrical Engineering, Purdue University;-
Venue:
IEEE Transactions on Computers
Year:
1987

Citing 17
Cited 0

An Introduction to GaAs Microprocessor Architecture for VLSI

Computer
A Survey of Advanced Microprocessors and HLL Computer Architectures

Computer
Structured computer organization; (2nd ed.)

Structured computer organization; (2nd ed.)
Advances in Computer Architecture

Advances in Computer Architecture
Computer Arithmetic: Principles, Architecture and Design

Computer Arithmetic: Principles, Architecture and Design
Computer Architecture and Parallel Processing

Computer Architecture and Parallel Processing
Bit-Slice Microprocessor Design

Bit-Slice Microprocessor Design
Very Long Instruction Word architectures and the ELI-512

ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
A user-microprogrammable, local host computer with low-level parallelism

ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
Hardware/software tradeoffs for increased performance

ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
Retrospective on high-level language computer architecture

ISCA '80 Proceedings of the 7th annual symposium on Computer Architecture
Organization and VLSI implementation of MIPS

Organization and VLSI implementation of MIPS
Assessing RJSCs In High-Level Language Support

IEEE Micro
The Types and Interactions of Vertical Migrations of Functions in a Multilevel Interpretive System

IEEE Transactions on Computers
Compilers and Computer Architecture

Computer
A VLSI RISC

Computer
The 801 minicomputer

IBM Journal of Research and Development

Quantified Score

Hi-index	14.98

Visualization

Abstract

This paper analyzes the potential performance of a high-level language (HLL) microprocessor architecture for special- purpose real-time applications. Our approach is based on mapping of HLL constructs into microcode, a concept called vertical migration. An analytical execution-time model of the reduced vertical-migration architecture is developed. It is applied to two different workload models: one corresponding to statement mixes, and the other showing some HLL kernel routines. Performance evaluation results are compared to different forms of the reduced vertical-migration architecture, and in various application domains. We underline in this paper the, basic relationships among microprocessor architecture, GaAs technology, and real-time applications.