An Instruction Issuing Approach to Enhancing Performance in Multiple Functional Unit Processors
IEEE Transactions on Computers
ACM SIGARCH Computer Architecture News
The IBM System/370 Vector Architecture: Design Considerations
IEEE Transactions on Computers
Available instruction-level parallelism for superscalar and superpipelined machines
ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems
IEEE Transactions on Computers
IBM RISC System/6000 processor architecture
IBM Journal of Research and Development
Instruction scheduling for the IBM RISC System/6000 processor
IBM Journal of Research and Development
Instruction-level parallelism from execution interlock collapsing
ACM SIGARCH Computer Architecture News
On the attributes of the SCISM organization
ACM SIGARCH Computer Architecture News
Interlock collapsing ALU for increased instruction-level parallelism
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
The Architecture of Symbolic Computers
The Architecture of Symbolic Computers
IEEE Transactions on Computers
High-Performance 3-1 Interlock Collapsing ALU's
IEEE Transactions on Computers
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A 32-bit 3-1 interlock collapsing ALU, proposed to allow the execution of two interlocked ALU-type instructions in one machine cycle using an instruction-level parallel machine implementation, is shown to produce results equivalent to a serial execution of the instructions using a 2-1 ALU. The equivalence is shown by deriving tables which represent all possible requirements for the serial execution of the instructions followed by the generalization of the table to represent sets of instructions rather than the individual instructions themselves. Consequently, the equivalence of the 3-1 interlock collapsing ALU operations with these generalized requirements of the serial execution of the instructions is shown. The correctness of a proposed high-speed interlock collapsing ALU is thereby demonstrated.