A bound analysis of scheduling instructions on pipelined processors with a maximal delay of one cycle

Authors:
Hong-Chich Chou;Chung-Ping Chung
Affiliations:
Institute of Computer Science and Information Engineering National Chiao Tung University Hsinchu, Taiwan 30050, ROC;Institute of Computer Science and Information Engineering National Chiao Tung University Hsinchu, Taiwan 30050, ROC
Venue:
Parallel Computing
Year:
1992

Citing 7
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Abstract

In this paper we study the problem of scheduling a set of partially ordered instructions with a maximal pipeline delay of one cycle on m processors (or functional units). The ultimate criterion is to minimize the execution of time of the set of instructions. This problem is NP-hard, hence we analyze the worst case of a greedy schedule, since the optimal schedule of this problem is also greedy. Let w"g and w"o be the completion times of an arbitrary greedy schedule and the optimal schedule respectively. We find that the bound is w"g/w"o =