Evaluation of a high performance code compression method

  • Authors:

  • Charles Lefurgy;Eva Piccininni;Trevor Mudge

  • Affiliations:

  • EECS Department, University of Michigan, 1301 Beal Ave., Ann Arbor, MI;EECS Department, University of Michigan, 1301 Beal Ave., Ann Arbor, MI;EECS Department, University of Michigan, 1301 Beal Ave., Ann Arbor, MI

  • Venue:
  • Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
  • Year:
  • 1999

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Abstract

Compressing the instructions of an embedded program is important for cost-sensitive low-power control-oriented embedded computing. A number of compression schemes have been proposed to reduce program size. However, the increased instruction density has an accompanying performance cost because the instructions must be decompressed before execution. In this paper, we investigate the performance penalty of a hardware-managed code compression algorithm recently introduced in IBM's PowerPC 405. This scheme is the first to combine many previously proposed code compression techniques, making it an ideal candidate for study. We find that code compression with appropriate hardware optimizations does not have to incur much performance loss. Furthermore, our studies show this holds for architectures with a wide range of memory configurations and issue widths. Surprisingly, we find that a performance increase over native code is achievable in many situations.