Executing compressed programs on an embedded RISC architecture
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Procedure based program compression
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Enhanced code compression for embedded RISC processors
Proceedings of the ACM SIGPLAN 1999 conference on Programming language design and implementation
Evaluation of a high performance code compression method
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Compiler techniques for code compaction
ACM Transactions on Programming Languages and Systems (TOPLAS)
Computers and Intractability; A Guide to the Theory of NP-Completeness
Computers and Intractability; A Guide to the Theory of NP-Completeness
Code density optimization for embedded DSP processors using data compression techniques
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
DISE: a programmable macro engine for customizing applications
Proceedings of the 30th annual international symposium on Computer architecture
An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs
Proceedings of the conference on Design, automation and test in Europe
A decompression core for powerPC
IBM Journal of Research and Development
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A cycle-accurate compilation algorithm for custom pipelined datapaths
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Using minimal minterms to represent programmability
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Generic netlist representation for system and PE level design exploration
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Proceedings of the conference on Design, automation and test in Europe
C-based design flow: a case study on G.729A for voice over internet protocol (VoIP)
Proceedings of the 45th annual Design Automation Conference
Automatic architecture refinement techniques for customizing processing elements
Proceedings of the 45th annual Design Automation Conference
Processor Description Languages
Processor Description Languages
A Flexible Code Compression Scheme Using Partitioned Look-Up Tables
HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
Bitmask-based control word compression for NISC architectures
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Squashing microcode stores to size in embedded systems while delivering rapid microcode accesses
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
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Shrinking time-to-market and high demand for productivity has driven traditional hardware designers to use design methodologies that start from high-level languages. However, meeting timing constraints of automatically generated IPs is often a challenging and time-consuming task that must be repeated every time the specification is modified. To address this issue, a new generation of IP-design technologies that is capable of generating custom datapaths as well as programming an existing one is developed. These technologies are often based on Horizontal Microcoded Architectures. Large code size is a well-know problem in HMAs, and is referred to as "code bloating" problem.In this paper, we study the code size of one of the new HMA-based technologies called NISC. We show that NISC code size can be several times larger than a typical RISC processor, and we propose several low-overhead dictionary-based code compression techniques to reduce the code size. Our compression algorithm leverages the knowledge of "don't care" values in the control words to better compress the content of dictionary memories. Our experiments show that by selecting proper memory architectures the code size of NISC can be reduced by 70% (i.e. 3.3 times) at cost of only 9% performance degradation. We also show that some code compression techniques may increase number of utilized block RAMs in FPGA-based implementations. To address this issue, we propose combining dictionaries and implementing them using embedded dual-port memories.