Executing compressed programs on an embedded RISC architecture
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Architectural partitioning of control memory for application specific programmable processors
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A case study in using two-level control stores
MICRO 20 Proceedings of the 20th annual workshop on Microprogramming
Improving code density using compression techniques
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Code compression based on operand factorization
MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture
Evaluation of a high performance code compression method
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
The Organization of Microprogram Stores
ACM Computing Surveys (CSUR)
An environment for research in microprogramming and emulation
Communications of the ACM
Expression-tree-based algorithms for code compresion on embedded RISC architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 11th international symposium on system-level synthesis and design (ISSS'98)
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Code compression for VLIW processors using variable-to-fixed coding
Proceedings of the 15th international symposium on System Synthesis
An analysis of code density for the two level programmable control of the Nanodata QM-1
MICRO 10 Proceedings of the 10th annual workshop on Microprogramming
Microprogrammed implementation of a single chip microprocessor
MICRO 11 Proceedings of the 11th annual workshop on Microprogramming
Enhanced compression techniques to simplify program decompression and execution
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Trace Scheduling: A Technique for Global Microcode Compaction
IEEE Transactions on Computers
Microprogramming: Perspective and Status
IEEE Transactions on Computers
An algorithm for minimizing read only memories for machine control
SWAT '68 Proceedings of the 9th Annual Symposium on Switching and Automata Theory (swat 1968)
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Modern microprocessors have used microcode as a way to implement legacy (rarely used) instructions, add new ISA features and enable patches to an existing design. As more features are added to processors (e.g. protection and virtualization), area and power costs associated with the microcode memory increased significantly. A recent Intel internal design targeted at low power and small footprint has estimated the costs of the microcode ROM to approach 20% of the total die area (and associated power consumption). Moreover, with the adoption of multicore architectures, the impact of microcode memory size on the chip area has become relevant, forcing industry to revisit the microcode size problem. A solution to address this problem is to store the microcode in a compressed form and decompress it at runtime. This paper describes techniques for microcode compression that achieve significant area and power savings, while proposes a streamlined architecture that enables high throughput within the constraints of a high performance CPU. The paper presents results for microcode compression on several commercial CPU designs which demonstrates compression ratios ranging from 50 to 62%. In addition, it proposes techniques that enable the reuse of (pre-validated) hardware building blocks that can considerably reduce the cost and design time of the microcode decompression engine in real-world designs.