Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer

Power analysis of a 32-bit RISC microcontroller integrated with a 16-bit DSP

ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design

Aggressive Dynamic Execution of Decoded Traces

Journal of VLSI Signal Processing Systems - Special issue on the 1997 IEEE workshop on signal processing systems (SiPS): design and implementation

Aggressive Dynamic Execution of Multimedia Kernel Traces

IPPS '98 Proceedings of the 12th. International Parallel Processing Symposium on International Parallel Processing Symposium

Scheduling Reusable Instructions for Power Reduction

Proceedings of the conference on Design, automation and test in Europe - Volume 1

Optimizing the Thermal Behavior of Subarrayed Data Caches

ICCD '05 Proceedings of the 2005 International Conference on Computer Design

Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-configurable Encoding

Journal of VLSI Signal Processing Systems

Profile-based dynamic pipeline scaling

The Journal of Supercomputing

Compiler support for dynamic pipeline scaling

EUC'07 Proceedings of the 2007 international conference on Embedded and ubiquitous computing

Inter-warp instruction temporal locality in deep-multithreaded GPUs

ARCS'13 Proceedings of the 26th international conference on Architecture of Computing Systems