Instruction fetch mechanisms for VLIW architectures with compressed encodings
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
Improving code density using compression techniques
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
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The SimpleScalar tool set, version 2.0
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A text-compression-based method for code size minimization in embedded systems
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Enhanced code compression for embedded RISC processors
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Compiler-driven cached code compression schemes for embedded ILP processors
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Compiler techniques for code compaction
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Alto: a link-time optimizer for the Compaq alpha
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Profile-guided code compression
PLDI '02 Proceedings of the ACM SIGPLAN 2002 Conference on Programming language design and implementation
Computers and Intractability: A Guide to the Theory of NP-Completeness
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Random Access Decompression using Binary Arithmetic Coding
DCC '99 Proceedings of the Conference on Data Compression
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Proceedings of the 30th annual international symposium on Computer architecture
Code generation and optimization for embedded digital signal processors
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Efficient execution of compressed programs
Efficient execution of compressed programs
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A dictionary construction technique for code compression systems with echo instructions
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Enhanced code density of embedded CISC processors with echo technology
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Link-time binary rewriting techniques for program compaction
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An instruction for direct interpretation of LZ77-compressed programs
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IBM Journal of Research and Development
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ACM Transactions on Programming Languages and Systems (TOPLAS)
Addressing instruction fetch bottlenecks by using an instruction register file
Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Merged Dictionary Code Compression for FPGA Implementation of Custom Microcoded PEs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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Electronic Notes in Theoretical Computer Science (ENTCS)
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Proceedings of the 7th annual IEEE/ACM International Symposium on Code Generation and Optimization
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ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Profile-driven selective program loading
EuroPar'10 Proceedings of the 16th international Euro-Par conference on Parallel processing: Part I
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In an embedded system, the cost of storing a program on-chip can be as high as the cost of a microprocessor. Compressing an application's code to reduce the amount of memory required is an attractive way to decrease costs. In this paper, we examine an executable form of program compression using echo instructions.With echo instructions, two or more similar, but not necessarily identical, sections of code can be reduced to a single copy of the repeating code. The single copy is left in the location of one of the original sections of the code. All the other sections are replaced with a single echo instruction that tells the processor to execute a subset of the instructions from the single copy.We present results of using echo instructions from a full compiler and simulator implementation that takes input programs, compresses them with echo instructions, and simulates their execution. We apply register renaming and instruction scheduling to expose more similarities in code, use profiles to guide compression, and propose minor architectural modifications to support echo instructions. In addition, we compare and combine echo instructions with two prior compression techniques: procedural abstraction and IBM's CodePac.