Enhanced code density of embedded CISC processors with echo technology

Authors:
Youfeng Wu;Mauricio Breternitz, Jr.;Herbert Hum;Ramesh Peri;Jay Pickett
Affiliations:
Intel Labs, Clara, CA;Intel Labs, Clara, CA;Intel Labs, Clara, CA;Intel Labs, Clara, CA;Intel Labs, Clara, CA
Venue:
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Year:
2005

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Abstract

Code density is an important issue in memory constrained systems. Some RISC processor, e.g. the THUMB extension in the ARM processor, supports aggressive code size reduction even at the cost of significant performance loss. In this paper, we develop an algorithm that utilizes a set of novel variable length Echo instructions and evaluate its effectiveness for IA32 binaries. Our experiments show that IA32 processor equipped with Echo instructions is capable of achieving a similar code density as the THUMB extension in the ARM instruction set with significantly lower performance penalty.