MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
The SimpleScalar tool set, version 2.0
ACM SIGARCH Computer Architecture News
ARM Architecture Reference Manual
ARM Architecture Reference Manual
ARM System Architecture
Using Complete Machine Simulation for Software Power Estimation: The SoftWatt Approach
HPCA '02 Proceedings of the 8th International Symposium on High-Performance Computer Architecture
Enhancing the performance of 16-bit code using augmenting instructions
Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems
Communications of the ACM - Program compaction
Simple offset assignment in presence of subword data
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
XTREM: a power simulator for the Intel XScale® core
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Hardware-managed register allocation for embedded processors
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Power-aware compilation for register file energy reduction
International Journal of Parallel Programming - Special issue: Workshop on application specific processors (WASP)
Application-level prediction of battery dissipation
Proceedings of the 2004 international symposium on Low power electronics and design
Dynamic coalescing for 16-bit instructions
ACM Transactions on Embedded Computing Systems (TECS)
Differential register allocation
Proceedings of the 2005 ACM SIGPLAN conference on Programming language design and implementation
Partitioning Variables across Register Windows to Reduce Spill Code in a Low-Power Processor
IEEE Transactions on Computers
M-ECho: a middleware for morphable data-streaming in pervasive systems
EESR '05 Proceedings of the 2005 workshop on End-to-end, sense-and-respond systems, applications and services
Enhanced code density of embedded CISC processors with echo technology
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Link-time binary rewriting techniques for program compaction
ACM Transactions on Programming Languages and Systems (TOPLAS)
Efficient Use of Invisible Registers in Thumb Code
Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture
Simultaneously improving code size, performance, and energy in embedded processors
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Allocating architected registers through differential encoding
ACM Transactions on Programming Languages and Systems (TOPLAS)
Selective code transformation for dual instruction set processors
ACM Transactions on Embedded Computing Systems (TECS) - SPECIAL ISSUE SCOPES 2005
Efficient code size reduction without performance loss
Proceedings of the 2007 ACM symposium on Applied computing
Stack size reduction of recursive programs
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
A design framework for real-time embedded systems with code size and energy constraints
ACM Transactions on Embedded Computing Systems (TECS)
Multithreading extension for Thumb ISA and decoder support
EHAC'06 Proceedings of the 5th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications
NISD: A Framework for Automatic Narrow Instruction Set Design
ICESS '07 Proceedings of the 3rd international conference on Embedded Software and Systems
Compiler Support for Code Size Reduction Using a Queue-Based Processor
Transactions on High-Performance Embedded Architectures and Compilers II
Compiling for Reduced Bit-Width Queue Processors
Journal of Signal Processing Systems
Code compaction of matching single-entry multiple-exit regions
SAS'03 Proceedings of the 10th international conference on Static analysis
Proceedings of the 8th annual IEEE/ACM international symposium on Code generation and optimization
EUC'07 Proceedings of the 2007 international conference on Embedded and ubiquitous computing
Two versions of architectures for dynamic implied addressing mode
Journal of Systems Architecture: the EUROMICRO Journal
Instruction selection for ARM/Thumb processors based on a multi-objective ant algorithm
CSR'06 Proceedings of the First international computer science conference on Theory and Applications
Reducing instruction bit-width for low-power VLIW architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Effective code discovery for ARM/Thumb mixed ISA binaries in a static binary translator
Proceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems
| Hi-index | 0.00 |
The ARM processor core is a leading processor design for the embedded domain. In the embedded domain, both memory and energy are important concerns. For this reason the 32 bit ARM processor also supports the 16 bit Thumb instruction set. For a given program, typically the Thumb code is smaller than the ARM code. Therefore by using Thumb code the I-cache activity, and hence the energy consumed by the I-cache, can be reduced. However, the limitations of the Thumb instruction set, in comparison to the ARM instruction set, can often lead to generation of poorer quality code. Thus, while Thumb code may be smaller than ARM code, it may perform poorly and thus may not lead to overall energy savings.