Multithreading extension for Thumb ISA and decoder support

Authors:
Lan Dong;Zhenzhou Ji;Guangzuo Cui;Mingzeng Hu
Affiliations:
Department of Computer Science and Technology, Harbin Institute of Technology, Harbin, China;Department of Computer Science and Technology, Harbin Institute of Technology, Harbin, China;Modern Education Technology Center, The Peking University, Harbin, China;Department of Computer Science and Technology, Harbin Institute of Technology, Harbin, China
Venue:
EHAC'06 Proceedings of the 5th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications
Year:
2006

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Abstract

Dual width instruction set embedded processors such as ARM provide 16-bit instruction set in addition to the 32-bit instructions set for lower energy and memory cost. The combination of hardware multithreading technique with the 16-bit code design can provide a tradeoff between performance and code size. In this paper, extension thread switch instruction (Ts) is added to the Thumb instruction set. With the decoder supporting, no extra cycles are needed to handle the Ts instructions. From analysis, our approach is a more flexible thread switch mechanism and provides better performance with little extra hardware cost.