The SPARC architecture manual: version 8
The SPARC architecture manual: version 8
Register connection: a new approach to adding registers into instruction set architectures
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Proceedings of the eighth international conference on Architectural support for programming languages and operating systems
Two-level hierarchical register file organization for VLIW processors
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Profile guided selection of ARM and thumb instructions
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
ARM System Architecture
An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs
Proceedings of the conference on Design, automation and test in Europe
Hardware-managed register allocation for embedded processors
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Dynamic coalescing for 16-bit instructions
ACM Transactions on Embedded Computing Systems (TECS)
Differential register allocation
Proceedings of the 2005 ACM SIGPLAN conference on Programming language design and implementation
Partitioning Variables across Register Windows to Reduce Spill Code in a Low-Power Processor
IEEE Transactions on Computers
CommBench-a telecommunications benchmark for network processors
ISPASS '00 Proceedings of the 2000 IEEE International Symposium on Performance Analysis of Systems and Software
Efficient code size reduction without performance loss
Proceedings of the 2007 ACM symposium on Applied computing
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The ARM processor is a dual width ISA processor that provides a 16-bit Thumb instruction set in addition to the 32-bit ARM instruction set. The compromises made in designing the Thumb instruction set leads to significantly increased instruction counts. This increase is in part due to the fact that only half of the register file is visible to most instructions in Thumb code. In this paper we address this inefficiency by providing a new instruction, the SetMask instruction, using which the compiler can change the visible subset of registers at any program point. Thus, through the use of this instruction the compiler can make use of all registers in all instructions. We present compiler techniques for allocating invisible registers and introducing SetMask instructions in a manner that the number of introduced instructions is minimized so that the increase in code size is insignificant. We implement this new instruction using the Dynamic Instruction Coalescing Framework which enables the SetMask instruction to have zero execution time cost. Our techniques eliminated 11.7% of MOV instructions from Thumb code while causing negligible code size increase.