Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Clustered Loop Buffer Organization for Low Energy VLIW Embedded Processors
IEEE Transactions on Computers
Journal of VLSI Signal Processing Systems
Instruction buffering exploration for low energy embedded processors
Journal of Embedded Computing - Low-power Embedded Systems
Embedded Systems Design
Hi-index | 0.00 |
We present extensions to the programmable DSP architectures for reduced power dissipations. These extensions address power reduction in both external and internal busses, which form a major component of power dissipation in pipelined programmable processors such as DSPs. We present two techniques to reduce power dissipation in the program and data memory address busses, a technique to reduce cross-coupling related power dissipation in the program memory data bus and a technique for reducing power dissipation in the input busses of the ALU. We present results in terms of power savings using these techniques.