Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
ACM Computing Surveys (CSUR)
Transition density, a stochastic measure of activity in digital circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power Optimization in VLSI Layout: A Survey
Journal of VLSI Signal Processing Systems
Low-power encodings for global communication in CMOS VLSI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Working-zone encoding for reducing the energy in microprocessor address buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A coding framework for low-power address and data busses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low power techniques for address encoding and memory allocation
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Low power address encoding using self-organizing lists
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Saving Power in the Control Path of Embedded Processors
IEEE Design & Test
GLS '97 Proceedings of the 7th Great Lakes Symposium on VLSI
Shade: A Fast Instruction Set Simulator for Execution Profiling
Shade: A Fast Instruction Set Simulator for Execution Profiling
Architectures and synthesis algorithms for power-efficient bus interfaces
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Loop scheduling with timing and switching-activity minimization for VLIW DSP
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
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Off-chip bus transitions are a major source of power dissipation for embedded systems. In this paper, new adaptive encoding schemes are proposed that significantly reduce transition activity on data and multiplexed address buses. These adaptive techniques are based on self-organizing lists to achieve reduction in transition activity by exploiting the spatial and temporal locality of the addresses. Also the proposed techniques do not require any extra bit lines and have minimal delay overhead. The techniques are evaluated for efficiency using a wide variety of application programs including SPEC 95 benchmark set. Unlike previous approaches that focus on instruction address buses, experiments demonstrate significant reduction in transition activity of up to 54% in data address buses and up to 59% in multiplexed address buses. The average reductions are twice those obtained using current schemes on a data address bus and more than twice those obtained on a multiplexed address bus.