Instruction-level parallelism in Prolog: analysis and architectural support
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Generating instruction sets and microarchitectures from applications
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Branch with masked squashing in superpipelined processors
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
Minimizing branch misprediction penalties for superpipelined processors
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
Synthesis of instruction sets for pipelined microprocessors
DAC '94 Proceedings of the 31st annual Design Automation Conference
Cache design trade-offs for power and performance optimization: a case study
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Fast Prolog with an extended general purpose architecture
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Saving Power in the Control Path of Embedded Processors
IEEE Design & Test
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This report describes a suite of benchmarks for Prolog implementation research. It includes an explanation of the format of the suite, which is meant to facilitate use of the benchmarks. The principal idea of this format is to maintain for each benchmark a master file from which particular instances - for particular Prolog execution systems, for particular statistics to capture, etc. - are generated automatically using a preprocessor. A preprocessor provided with the suite for this purpose is described, along with a related utility and a simple framework for execution time measurement. Source code for these is appended. Possibilities for future work with respect both to this suite and to Prolog benchmarking more generally are dis- cussed briefly. For each benchmark in the suite, source code and execution times under C Prolog and Quintus Prolog (compiled) on a Sun 3/60 are appended.