Reduced instruction set computer architectures for VLSI
Reduced instruction set computer architectures for VLSI
The design and evaluation of a high performance Smalltalk system
The design and evaluation of a high performance Smalltalk system
Tags and type checking in LISP: hardware and software approaches
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
RISCs vs. CISCs for Prolog: a case study
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
801 storage: architecture and programming
ACM Transactions on Computer Systems (TOCS)
The occur-check problem revisited
Journal of Logic Programming
A high-performance low risc machine for logic programming
Journal of Logic Programming
Improving the execution speed of compiled prolog with modes, clause selection, and determinism
II and Colloquium on Functional and Logic Programming and Specifications (CFLP) on TAPSOFT '87: Advanced Seminar on Foundations of Innovative Software Development
KCM: a knowledge crunching machine
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Can logic programming execute as fast as imperative programming?
Can logic programming execute as fast as imperative programming?
A High Performance Architecture for PROLOG
A High Performance Architecture for PROLOG
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
A Prolog Benchmark Suite for Aquarius
A Prolog Benchmark Suite for Aquarius
The Bottom-Up Design of a
Libra: a high performance balanced computer architecture for prolog
Libra: a high performance balanced computer architecture for prolog
Viewing instruction set design as an optimization problem
MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture
SPIRE: streaming processing with instructions release element
ACM SIGARCH Computer Architecture News
Instruction-level parallelism in Prolog: analysis and architectural support
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Branch with masked squashing in superpipelined processors
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
Minimizing branch misprediction penalties for superpipelined processors
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
Synthesis of instruction sets for pipelined microprocessors
DAC '94 Proceedings of the 31st annual Design Automation Conference
A tool for processor instruction set design
EURO-DAC '94 Proceedings of the conference on European design automation
An analysis of dynamic scheduling techniques for symbolic applications
MICRO 26 Proceedings of the 26th annual international symposium on Microarchitecture
Saving Power in the Control Path of Embedded Processors
IEEE Design & Test
The Instruction Set Architecture of the Inference Processor UNIRED II
PACT '93 Proceedings of the IFIP WG10.3. Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism
From simulation to practice: cache performance study of a Prolog system
Proceedings of the 2002 workshop on Memory system performance
Decomposition of instruction decoders for low-power designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Most Prolog machines have been based on specialized architectures. Our goal is to start with a general purpose architecture and determine a minimal set of extensions for high performance Prolog execution. We have developed both the architecture and optimizing compiler simultaneously, drawing on results of previous implementations. We find that most Prolog specific operations can be done satisfactorily in software; however, there is a crucial set of features that the architecture must support to achieve the best Prolog performance. The emphasis of this paper is on our architecture and instruction set. The costs and benefits of the special architectural features and instructions are analyzed. Simulated performance results are presented and indicate a peak compiled Prolog performance of 3.68 million logical inferences per second.