Programming in Prolog (2nd ed.)
Programming in Prolog (2nd ed.)
Bulldog: a compiler for VLSI architectures
Bulldog: a compiler for VLSI architectures
Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Logic for problem-solving
KCM: a knowledge crunching machine
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
A VLIW architecture for Prolog
IEEE Computer Society Technical Committee Newsletter on Microprogramming and Microarchitecture - Special double issue on design methods and architectures
Can logic programming execute as fast as imperative programming?
Can logic programming execute as fast as imperative programming?
An evaluation system for application specific architectures
MICRO 23 Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture
Fast Prolog with an extended general purpose architecture
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Optimizing Supercompilers for Supercomputers
Optimizing Supercompilers for Supercomputers
Very Long Instruction Word architectures and the ELI-512
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
A Prolog Benchmark Suite for Aquarius
A Prolog Benchmark Suite for Aquarius
Reduced Instruction Set Computer Architectures for VLSI
Reduced Instruction Set Computer Architectures for VLSI
Special- or General-Purpose Hardware for Prolog: A Comparison
Special- or General-Purpose Hardware for Prolog: A Comparison
A high performance architecture for prolog
A high performance architecture for prolog
An analysis of dynamic scheduling techniques for symbolic applications
MICRO 26 Proceedings of the 26th annual international symposium on Microarchitecture
Exploitation of Fine-grain Parallelism in Logic Languages on Massively Parallel Architectures
PACT '94 Proceedings of the IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques
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The demand of increasing computation power for symbolic processing has given a strong impulse to the development of ASICs dedicated to the execution of prolog. Unlike past microcoded implementation based on the Warren machine model, novel trends in high performance Prolog processors suggest the implementation of RISC-based processors committed to prolog only through the adoption of a few basic dedicated features, like the Berkeley Abstract Machine (BAM) processor.Following the idea of using a smart compiler for a simple instruction set, the SYMBOL project represents an experiment in applying global compaction techniques and VLIW design philosophy to the static exploitation of instruction-level parallelism in Prolog.This paper presents code analysis results and shows how we can approach the theoretical speed-up limit (about 3) imposed by Amdahl's law on shared memory models, by means of global code optimizations and a suitable architectural support. In addition, we show implementation details and some preliminary data of a VLSI prototype architecture.