Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-level power optimization of special purpose applications: the beach solution
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Low-power encodings for global communication in CMOS VLSI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
A coding framework for low-power address and data busses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power optimization of system-level address buses based on software profiling
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Code compression for low power embedded system design
Proceedings of the 37th Annual Design Automation Conference
Power-optimal encoding for a DRAM address bus
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Saving Power in the Control Path of Embedded Processors
IEEE Design & Test
GLS '97 Proceedings of the 7th Great Lakes Symposium on VLSI
Some Issues in Gray Code Addressing
GLSVLSI '96 Proceedings of the 6th Great Lakes Symposium on VLSI
Low-power instruction bus encoding for embedded processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Minimizing memory access energy in embedded systems by selective instruction compression
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Gray code bus encoding is a simple approach to reduce instruction address bus switching. It requires little encoding hardware and no additional bus lines. Our analytical study reveals that with Gray encoding the address bus switching can be reduced by nearly 50%, for long, sequentially accessed code. However, existing Gray bus encoding techniques involve decoding the Gray coded bus, which is expensive in terms of performance and area, and has stymied efforts to implement such a coding scheme in real systems. Furthermore, based on our experimental investigation on a set of benchmarks, the Gray bus encoding may be much less effective than expected - the switching reduction rate can be as low as under 30%. This paper presents a design approach to enable the use of Gray encoding by avoiding the bus decoding operation and to enhance the switching reduction efficiency by using a shifted Gray code for a given application. The experiment results show that our design approach can improve bus switching reduction rate by up to 22.55%, with little overhead on design logic and performance.