Low-energy for deep-submicron address buses
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Dynamic Power Management: Design Techniques and CAD Tools
Dynamic Power Management: Design Techniques and CAD Tools
HPCA '02 Proceedings of the 8th International Symposium on High-Performance Computer Architecture
DVS for On-Chip Bus Designs Based on Timing Error Correction
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
New Generation of Predictive Technology Model for Sub-45nm Design Exploration
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Exploiting Variable Cycle Transmission for Energy-Efficient On-Chip Interconnect Design
VLSID '08 Proceedings of the 21st International Conference on VLSI Design
Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques
ISVLSI '08 Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI
An interconnect-aware delay model for dynamic voltage scaling in NM technologies
Proceedings of the 19th ACM Great Lakes symposium on VLSI
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In this paper, design space exploration methods for interconnect repeaters in DSM power-managed VLSI are proposed. These methods guarantee that the designed interconnects are energy-optimal, while they meet their performance objectives in all the system operating states. These methods take the dynamic output resistance characteristic of the repeaters into account, when the system operating voltage and/or operating frequency requirement changes. Utilizing the proposed design methods, a multi-cycle bus is designed for some performance targets. HSPICE simulations confirm that the designed bus is energy-optimal, and it meets its performance objectives in all the system operating states.