Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
Dynamic Power Management in Wireless Sensor Networks
IEEE Design & Test
Design Challenges of Technology Scaling
IEEE Micro
New Generation of Predictive Technology Model for Sub-45nm Design Exploration
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
The limit of dynamic voltage scaling and insomniac dynamic voltage scaling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Repeater insertion in power-managed VLSI systems
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
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Employing microsystems with Dynamic Voltage Scaling (DVS) is an effective design solution to alleviate their energy consumption. The importance of such design technique keeps growing as both high-performance and low-energy consumption are simultaneously desirable. Existing Power Management Units (PMUs) that support DVS, mainly rely on the delay models valid for CMOS logic. In this work, we show that this may result into improper design and utilization of microsystems subject to DVS; as interconnect delay has become the dominant fraction of the total delay. In accordance with this design concern, we propose a modified delay model which encompasses the effect of interconnect parasitic components, and is suitable for accurate modeling, design and execution of DVS performed by PMUs in nanometer (nm) technologies. HSPICE simulations confirm that the proposed delay model is much more accurate when predicting the performance of a 4-section global H-Tree clock distribution network subject to voltage scaling. The error on predicted performance from true delays is reduced by up to a factor of 4.