Reducing cross-coupling among interconnect wires in deep-submicron datapath design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Reducing bus delay in submicron technology using coding
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Active shields: a new approach to shielding global wires
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Bus energy minimization by transition pattern coding (TPC) in deep sub-micron technologies
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Bus encoding to prevent crosstalk delay
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Formulae and applications of interconnect estimation considering shield insertion and net ordering
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Error-correction and crosstalk avoidance in DSM busses
Proceedings of the 2003 international workshop on System-level interconnect prediction
Optimal shielding/spacing metrics for low power design
ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
Analysis and Avoidance of Cross-Talk in On-Chip Buses
HOTI '01 Proceedings of the The Ninth Symposium on High Performance Interconnects
Analysis and Reduction of Capacitive Coupling Noise in High-Speed VLSI Circuits
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
A Crosstalk Aware Interconnect with Variable Cycle Transmission
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Exploiting Crosstalk to Speed up On-Chip Buses
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Area and Energy-Efficient Crosstalk Avoidance Codes for On-Chip Buses
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Delay and Energy Efficient Data Transmission for On-Chip Buses
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
Delay and peak power minimization for on-chip buses using temporal redundancy
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Coding for system-on-chip networks: a unified framework
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Bus encoding for simultaneous delay and energy optimization
Proceedings of the 13th international symposium on Low power electronics and design
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On-chip buses in deep-submicron designs have large propagation delay due to dominant coupling capacitance. As delay impacts system performance, several techniques have been proposed in literature to minimize it. A common point in most of the existing techniques is to consider uniformly distributed random data, but the propagation delay is data dependent and data is application dependent. Different applications may have different data behavior. The existing techniques which consider uniformly distributed random data may not exploit the exact data behavior of an application and hence can give different performance results. In this paper, by exploiting data behavior, we propose two on-chip delay minimization techniques, namely, data packing and data permutation. We validate our techniques by focusing on the L1 cache address/data buses using SPEC2000 CINT benchmarks. We show that, in the address bus case, the data packing and data permutation techniques achieve more than 2.3X and 1.6X speedup, respectively, over the unencoded bus, whereas in the case of data bus, both these techniques achieve more than 1.5X and 1.4X speedup, respectively. For a 32-bit bus, both data packing and data permutation techniques require 38 and 34 wires, respectively.