Delay and peak power minimization for on-chip buses using temporal redundancy
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Exploiting on-chip data behavior for delay minimization
Proceedings of the 2007 international workshop on System level interconnect prediction
Bus encoding schemes for minimizing delay in VLSI interconnects
Proceedings of the 20th annual conference on Integrated circuits and systems design
Bus encoding for simultaneous delay and energy optimization
Proceedings of the 13th international symposium on Low power electronics and design
Selective shielding technique to eliminate crosstalk transitions
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Delay-efficient bus encoding techniques
Microprocessors & Microsystems
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On-chip buses in deep sub-micron designs consume significant amounts of power and have large propagation delays. Thus, minimizing power consumption and propagation delay are the most important design objectives. In this paper, we propose a technique for delay and energy efficient data transmission for on-chip buses and evaluate the effectiveness of our technique by focusing on the L1 cache address/ data buses of a microprocessor using the SPEC2000 CINT benchmark suit. We show that our technique achieves 31% (30%) of delay improvement along with energy savings of (13%) 9% over the base case for data transmission on address (data) bus.