Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Information-theoretic bounds on average signal transition activity
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-string on-chip signaling techniques: effectiveness and robustness
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
System-in-package (SIP): challenges and opportunities
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Analysis and implementation of charge recycling for deep sub-micron buses
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Odd/even bus invert with two-phase transfer for buses with coupling
Proceedings of the 2002 international symposium on Low power electronics and design
Bus energy minimization by transition pattern coding (TPC) in deep sub-micron technologies
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Adaptive Bus Encoding Technique for Switching Activity Reduced Data Transfer over Wide System Buses
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Architectures and synthesis algorithms for power-efficient bus interfaces
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
EDA challenges facing future microprocessor design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multimode embedded compression codec engine for power-aware video coding system
IEEE Transactions on Circuits and Systems for Video Technology
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We present a novel coding scheme for reducing bus power dissipation. The presented approach is well suited to driving off-chip buses, where the line capacitance is a dominant factor. A distinctive feature of the technique is the dynamic reodering of bus line positions, in order to minimize the toggling activity on physical bus wires. The effectiveness of the approach is demonstrated through cycle-accurate simulation of industrial benchmarks in conjunction with post-layout evaluation of speed, power and area overhead.