ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Design considerations for databus charge recovery
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Analysis and implementation of charge recycling for deep sub-micron buses
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Low-energy off-chip SDRAM memory systems for embedded applications
ACM Transactions on Embedded Computing Systems (TECS)
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This paper presents in-order pulsed charge recycling to reduce energy consumption in an off-chip data bus. The proposed technique performs charge recycling by employing three different steps. At the beginning of an off-chip data bus transaction, i) connect all bus lines that are expected to fall to a common node, ii) connect, one at a time and for a fixed period of time, each of bus lines that are expected to rise to the same common node to enable charge recycling, and finally, iii) resume regular data bus transaction by enabling the tri-state buffers to complete the remaining charging (discharging) of the rising (falling) bus lines. Experimental results in Hspice show that the proposed technique achieves 17.4% average energy savings in a 32 bit-wide data bus implemented in a 0.13¼m technology with a 1.8V supply voltage.