System-level power estimation using an on-chip bus performance monitoring unit

  • Authors:
  • Youngjin Cho;Younghyun Kim;Sangyoung Park;Naehyuck Chang

  • Affiliations:
  • Seoul National University;Seoul National University;Seoul National University;Seoul National University

  • Venue:
  • Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
  • Year:
  • 2008

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Abstract

In this paper we propose an on-chip bus PMU which makes accurate estimates of system power consumption from a first-order linear power model by utilizing system-level activity information exchanged on the on-chip bus. It can easily be customized for different on-chip and off-chip memory devices, and is not dependent on a specific CPU core. We model memory devices using energy state machines, describe them in XML, and use that description automatic synthesis of the PMU. We compare the short-term accuracy of the proposed PMU with a cycle-accurate system-level power estimator, and assess its long-term accuracy with a real hardware prototype. Experimental results show that the the power estimation deviates less than 5% from real measurements.