A dynamic-SDRAM-mode-control scheme for low-power systems with a 32-bit RISC CPU

Authors:
Seiji Miura;Kazushige Ayukawa;Takao Watanabe
Affiliations:
Central Research Laboratory, Hitachi, Ltd., 1-280 Higashi-koigakubo, Kokubunji-shi, Tokyo 185-8601, Japan;Central Research Laboratory, Hitachi, Ltd., 1-280 Higashi-koigakubo, Kokubunji-shi, Tokyo 185-8601, Japan;Central Research Laboratory, Hitachi, Ltd., 1-280 Higashi-koigakubo, Kokubunji-shi, Tokyo 185-8601, Japan
Venue:
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Year:
2001

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