The SPLASH-2 programs: characterization and methodological considerations
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Noise in deep submicron digital design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Power supply noise analysis methodology for deep-submicron VLSI chip design
DAC '97 Proceedings of the 34th annual Design Automation Conference
Digital systems engineering
Fault modeling and simulation for crosstalk in system-on-chip interconnects
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Noise-aware power optimization for on-chip interconnect
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Reliable low-power design in the presence of deep submicron noise (embedded tutorial session)
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Toward achieving energy efficiency in presence of deep submicron noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multiprocessor enhancements of the SimpleScalar tool set
ACM SIGARCH Computer Architecture News
Soft digital signal processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Digital Design: Principles and Practices
Digital Design: Principles and Practices
An adaptive low-power transmission scheme for on-chip networks
Proceedings of the 15th international symposium on System Synthesis
Low Power Error Resilient Encoding for On-Chip Data Buses
Proceedings of the conference on Design, automation and test in Europe
Quality-of-service and error control techniques for network-on-chip architectures
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Energy-aware deterministic fault tolerance in distributed real-time embedded systems
Proceedings of the 41st annual Design Automation Conference
Leakage-and crosstalk-aware bus encoding for total power reduction
Proceedings of the 41st annual Design Automation Conference
Gate-Level Mitigation Techniques for Neutron-Induced Soft Error Rate
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Quality-of-service and error control techniques for mesh-based network-on-chip architectures
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
A robust self-calibrating transmission scheme for on-chip networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Self-Adaptive Networked Entities for Building Pervasive Computing Architectures
ICES '08 Proceedings of the 8th international conference on Evolvable Systems: From Biology to Hardware
Quality-of-service and error control techniques for mesh-based network-on-chip architectures
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Transient and Permanent Error Co-management Method for Reliable Networks-on-Chip
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Self-adaptive system for addressing permanent errors in on-chip interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Spatio-temporal coding to improve speed and noise tolerance of on-chip interconnect
Microelectronics Journal
Optimizing power and performance for reliable on-chip networks
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Bus encoding for total power reduction using a leakage-aware buffer configuration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dual-layer adaptive error control for network-on-chip links
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy-aware fault-tolerant network-on-chips for addressing multiple traffic classes
Microprocessors & Microsystems
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With dramatic scaling in feature sizes, noise resilience is becomingone of the most important design parameters, similar to performanceand energy efficiency. Noise resilience is particularly problematicin long on-chip buses of complex single chip systems suchas on-chip multiprocessors. While one might opt to employ a verypowerful error protection scheme, this may not be very energy efficientas noise behavior typically varies over time. In this paper, wepropose an adaptive error protection scheme for energy efficiency,where the type of the coding scheme is modulated dynamically.The idea behind this strategy is to monitor the dynamic variationsin noise behavior and use the least powerful (and hence the mostenergy efficient) error protection scheme required to maintain theerror rates below a pre-set threshold. Our detailed experimental resultsobtained through simulation show that this adaptive strategyachieves the same level of error protection as the most powerfulstrategy experimented, without experiencing the latter's energy inefficiency.Based on our results, we recommend system designersto adopt adaptive protection schemes in environments where bothenergy and reliability are important.