IBM experiments in soft fails in computer electronics (1978–1994)
IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors
IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors
Critical charge calculations for a bipolar SRAM array
IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Evaluation of a Soft Error Tolerance Technique Based on Time and/or Space Redundancy
SBCCI '00 Proceedings of the 13th symposium on Integrated circuits and systems design
The Effect of Threshold Voltages on the Soft Error Rate
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Adapative Error Protection for Energy Efficiency
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Critical charge and set pulse widths for combinational logic in commercial 90nm cmos technology
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Soft Error Rate Reduction Using Circuit Optimization and Transient Filter Insertion
Journal of Electronic Testing: Theory and Applications
False Error Vulnerability Study of On-line Soft Error Detection Mechanisms
Journal of Electronic Testing: Theory and Applications
Design of asynchronous circuits for high soft error tolerance in deep submicrometer CMOS circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Neutron-induced single-event upsets have become increasingly problematic in aggressively scaled process technologies due to smaller nodal capacitances and reduced operating voltages. We present a probability-based analysis of neutron strikes on combinational logic chains and investigate techniques to increase circuit robustness in terms of decreasing the probability of upsetting the capturing latch given a particle strike. We show that using a technique of inserting simple cross-coupled inverter pairs on error prone sites, as well as intelligently placing lower Vth devices and readjusting device width, can increase the robustness by nearly 20% thereby increasing the mean time between soft errors by almost 25%. This technique incurs substantially less overhead than traditional redundancy approaches to mitigating soft errors.