Reliable low-power design in the presence of deep submicron noise (embedded tutorial session)

Authors:
Naresh Shanbhag;K. Soumyanath;Samuel Martin
Affiliations:
Coordinated Science Lab, ECE Department, University of Illinois at Urbana-Champaign, Urbana, IL;Circuits Research Lab, Intel Corporation, Hillsboro, OR;Bell Labs, Lucent Technologies, Murray Hill, NJ
Venue:
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Year:
2000

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Abstract

Scaling of feature size in semiconductor technology has been responsible for increasingly higher computational capacity of silicon. This has been the driver for the revolution in communications and computing. However, questions regarding the limits of scaling (and hence Moore's Law) have arisen in recent years due to the emergence of deep submicron noise. The tutorial describes noise in deep submicron CMOS and their impact on digital as well as analog circuits. In particular, noise-tolerance is proposed as an effective means for achieving energy and performance efficiency in the presence of DSM noise.